As background for our invention computer systems use arrays to store information and these arrays are sometimes subject to hardware errors: individual array cell, bitline, wordline, etc.. In the related applications there is described ABIST (Array Built-In Self Test) microprocessors used to test and characterize on-chip arrays. This application addresses a system and method for testing and characterizing on-chip arrays in engineering, manufacturing, or burn-in environments with programmable test patterns. In general, during manufacturing of a computer system integrated circuit arrays are tested by providing a known data input at a known address to the array and comparing the output to the expected output. One well- known and widely used prior art system for testing integrated circuit logic, particularly integrated circuit memory arrays, is to form a dedicated test circuit on the chip with the array itself. This is called Array Built-In Self Test (ABIST).
An early example of ABIST technology, one that allowed elimination of an alternative microprocessor self test via a PLA LSSD test with I/O isolation of RAM functional test with no performance measurement, is represented by U.S. Pat. No. 4,841,485, granted Jun. 20, 1989 to R. J. Prilik et al, and assigned to International Business Machines Corp. This basic patent provided a memory array of bistable memory cells connectable to two different voltages that will operate when biased with both voltages at the same level in a bistable mode, and when biased at different voltage levels, will operate in an embedded self test binary pattern mode. The uses of this base technology also has been explored by others. Some related ABIST developments have been referenced above in the related pending applications of the assignee. There have been IBM Publications also relating to the area, including the IBM Journal of Research and Development article R. W. Bassett et al, "Boundary-Scann Design Principles for Efficient LSSD ASIC Testing, Vol. 34, No.2/3 March/May, 1990. Other IBM patents in the field include U.S. Pat. Nos. 5,442,641; 5,173,906 and 5,386,392.
With the many inventions in this field which have been made, this technology now allows high speed testing of the array without having to force correspondence between the array and the input/output connections to the chip itself.
U.S. Pat. No. 5,173,906 to Dreibelbis et al, issued Dec. 22, 1992, provides a BIST (Built-In Self Test) function for VLSI logic or memory module which is programmable. This circuitry is provided with a looping capability to enable enhanced burn-in testing. An on-chip test arrangement for VLSI circuits is provided with programmable data pattern sequences wherein the data patterns are selectable via instruction code in order to reduce the probability of self test redesign. However, this Dreibelbis patent does not provide flexibility to test VLSI circuits with any and all tests which can be required to test both static and dynamic arrays, in accordance with the invention claimed in the prior related application, U.S. Ser. No. 08/450,585 Filed May 31, 1995, by Turgeon et al, entitled "Programmable Built-In Self Test Method and Controller for Arrays". Generally, this prior application is our preferred ABIST embodiment for the present application representing an ABIST that has the programmable ability to test and identify defective array locations and using our invention to take corrective action.
The prior application disclosing our preferred ABIST embodiment in this application is being illustrated in a preferred manner for enabling the testing of arrays having two different logical views, one for READ mode, and one basically for WRITE mode.